1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device with a contact plug (referred to as a bit line contact plug) for bit line connection and a method of fabricating the same.
2. Description of the Related Art
Because device patterns are minute, bit line contact plugs are separately formed in a cell region, a core region, and a peripheral circuit region when performing conventional 8F2 DRAM processing. This is because of the large differences in the etching targets. That is, only an oxide layer used as an interlayer insulating layer is etched to be a slight etching target when a contact hole for a bit line contact plug is formed in a cell region. On the other hand, when a contact hole for a bit line contact plug in core and peripheral circuit regions are formed, an etching process is performed further down to the level of a silicon nitride layer used as a gate hard mask and an active region of a semiconductor substrate. Because the contact holes in the cell region and the contact holes in the core and peripheral circuit regions must be separately formed, a plurality of photoresist patterns are required, which complicate the overall fabrication process and increase the manufacturing costs.
Therefore, a method of forming a contact hole is suggested, in which a condition with a high etching selectivity is developed to merge the forming of the contact hole that exposes a contact of the cell region and which further exposes the source/drain of an NMOS of the core and peripheral circuit regions. Then, a contact hole to expose a gate conductive layer on the core and peripheral circuit regions, and a contact hole to expose the source/drain of the PMOS of the core and peripheral circuit regions, are formed.
However, as DRAMs become more highly integrated, the structure is changed from 8F2 to 6F2. In the 6F2 structure, a core region layout less than a design rule is required. This in turn makes cell region processing become more difficult when forming a bit line contact plug because of the complicate requirements involved.
In particular, because the bit line contact plug in the cell region is closer to a storage node contact plug than in an 8F2 structure, a spacer must be formed to prevent a short from being formed between the storage node contact plug and the bit line contact plug. However, a contact plug connected to a gate conductive layer on the core and peripheral circuit regions usually has no spacer for decreasing contact resistance because the spacer reduces the contact area. Furthermore, the contact plug connected to the source/drain of the NMOS of the peripheral circuit region and the contact plug connected to the source/drain of the PMOS of the core region may be formed by a conventional method. However, the contact plug connected to the source/drain of the NMOS of the core region, and the contact plug connected to the source/drain of the PMOS are formed by a self-aligned contact (SAC) technique. Accordingly, the contact plug connected to the source/drain of the NMOS of the core and to the peripheral circuit regions is different from the contact plug connected to the source/drain of the PMOS.
In addition, ion implantation used to form a plug layer of high concentration is performed to reduce contact resistance by supplementing dopants lost after the contact hole etching. But because the plug layer is closer to a channel in the case of a contact hole formed by the SAC technique it has an effect on the channel (i.e., a plug effect). Due to this fact, ion implantation to the plug layer cannot be performed simultaneously with the formation of both the contact holes embodied by the SAC and a typically formed contact hole, thereby complicating the overall fabrication process.
Thus, when forming a bit line contact plug of a 6F2 DRAM under current practices, a bit line contact hole in a cell region is first formed. A contact hole that exposes a source/drain of an NMOS of a core region and a contact hole that exposes a source/drain of a PMOS are respectively formed by the SAC technique. Thereafter, a contact hole that exposes a source/drain of an NMOS of a peripheral circuit region, and a contact hole that exposes of source/drain of a PMOS are respectively formed by the SAC technique. Then, the ion implantation is performed to respective contact holes to form an N+ type plug layer and a P+ type plug layer. Therefore, in 6F2 DRAM, the separate kinds of the contact holes formed require forming a photoresist pattern 5˜6 times, thereby complicating the overall fabrication process and increasing the manufacturing costs.